The present invention relates to a data transmission circuit for use in semiconductor memory devices, and more particularly relates to an improved data transmission circuit for transmitting data signals from a data input buffer to a pair of input/output (herein referred to as "I/O") bus lines in a complementary metal oxide semiconductor (CMOS) dynamic random access memory (hereinafter referred to as a "DRAM") device.
Conventionally, a CMOS DRAM device includes the data input buffer which is activated in a write cycle and converts TTL (Transistor-Transistor Logic) level input data signals to CMOS logic level data signals. The data input buffer supplies true and complement output data signals on a pair of data bus lines, respectively, and signals on the pair of data bus lines are respectively sent to a pair of I/O bus lines. Thereafter, the true and complement data signals on the I/O bus lines are respectively transmitted via a sense amplifier to a pair of corresponding bit lines via a pair of transfer gates; the transfer gates are respectively coupled to the I/O bus lines and turned on by a column address signal. One of the true and complement data signals on the bit line pair is written into one memory cell selected by a row address signal provided by a row address decoder.
However, in high density DRAM device, such as a one mega-bit DRAM, both the data bus line pair and the I/O bus line pair extend a long distance from the data input buffer to the bit line pair. In view of this circuit arrangement, the data input buffer must bear the burden of driving one of the data bus line pairs having parasitic capacitance of approximately 1.5 Pf per line and the corresponding I/O bus line having about 3 Pf to 4 Pf per line as a load.
To assist in understanding the disadvantages which plague prior art devices, a data transmission circuit is shown in a block diagram form in FIG. 1. Referring to FIG. 1, the data signal read into the circuit through the data input buffer 10 is output as a pair of true and complement MOS logic level data signals DIN and DIN, and the signals DIN and DIN are respectively coupled to a pair of data bus lines 11 and 12. The signals DIN and DIN are respectively sent on the I/O bus lines 13 and 14 through a pair of transmission transistors 1 and 2 which are turned on by the transfer gate control clock signal CCS on a gate line 16 generated with the combination of a write enable signal and column address signals. The data signals transmitted on the I/O bus lines 13 and 14 are respectively sent on a pair of bit lines 61 and 60 through a pair of transmission transistors 44 and 43 constituting a transfer gate 40 turned on by the column address signal CS on a gate line 41 and through a sense amplifier 50. Thereafter, one of the true and complement data signals on the bit lines 61 or 60 is written into a memory cell 63 or 62 by a row address signal on a row address line 65 or 64.
An I/O sense amplifier 30 operated during only a read cycle amplifies one of the true and complement data signals on the I/O bus lines 13 and 14 read out from the memory cells. An equalizer circuit 20 begins the operation for equalizing the I/O bus lines 13 and 14 at the precharge time of read and write cycles.
Therefore, the data transmission circuit shown in FIG. 1 must drive the large parasitic capacitance of the data bus line and its corresponding I/O bus line as a load in order to write data information into a memory cell 62 or 63.
Therefore, the data input buffer must include a large size current drive transistor at the output stage thereof in order to charge the large parasitic capacitance and as a result, a low rate transfer speed and the large power consumption are effected.
One way of decreasing the parasitic capacitance of the I/O bus line providing the largest capacitance was to divide on chip all memory cells into several blocks including a certain number of memory cells according to the integration and density of memory cells. Such increase of the number of divided blocks causes an increase of I/O bus line pairs and that of their corresponding transmission transistors.
In a write cycle for transferring the data information into the memory cell array, however many are the I/O bus line pairs due to the number of such divided blocks, there is no problem because only one of the I/O bus line pairs is selected and then one of the data signals on the selected I/O bus line pair is stored in an addressed memory cell. However, the larger the integration density of memory cells, the more serious is the problem of testing the memory cells when the memory device is manufactured. That is, the test time for writing data information into all memory cells and for reading the stored information out from each memory cell increases greatly according to the increased density of memory cells. Therefore, to achieve a high speed test of memory cells, a plurality of data bits must be written into addressed memory cells and read out from those memory cells. In this case, since the I/O bus line pairs must be coupled to the data input buffer in the same numbers as the number of data bits written into memory cells, the load burden of the data input buffer will be increased by the number of such data bits. Finally the size of the transistors for driving the I/O bus pairs at the output stage of the data input buffer will be increased to accommodate the increased parasitic capacitance and as a result, the chip size will be increased.
The data transmission circuit for solving the predescribed problems, as shown in FIG. 5, is disclosed in an U.S. patent application Ser. No. 067,016 entitled "Data Transmission Circuit", which is now U.S. Pat. No. 4,757,215 allowed to SEO SEUNG-MO and assigned to the present applicant. Referring to FIG. 5, inverting buffer circuits 70 and 80 for isolating data bus lines 11 and 12 and I/O bus lines 13 and 14 are respectively coupled between transmission gates 1 and 2 and data bus lines 13 and 14. In a precharge cycle, all of transmission gates 1 and 2 and inverting buffer circuits 70 and 80 will remain at off-states in response to a write data clock .phi.WDT applied via inverter 600 to control electrodes of transmission gates 1 and 2, and both of I/O bus lines 13 and 14 will be precharged to a potential VDD through the operation of the precharge and equalizing circuit. In a write cycle, after data DIN and DIN from the data input buffer 10 are respectively supplied to data bus lines 11 and 12, in response to the clock .phi.WDT, transmission gates 1 and 2 and inverting buffer circuits 70 and 80 are all operated to transmit inverted data DIN and DIN on I/O bus lines 13 and 14 respectively. Therefore, a decreased load burden of the data input buffer will be accomplished because of the treatment of only data bus lines 11 and 12 as loads. This data transmission circuit has no problem in such a precharge scheme that I/O bus lines 13 and 14 are precharged at a full power supply potential VDD. However, where I/O bus lines 13 and 14 are precharged at a half potential, that is, at a potential having an amplitude of 1/2VDD, the transmission circuit has a drawback in circuit operation. That is, in a precharge cycle, P-channel MOS transistors 72 and 82 are all turned on due to a 1/2VDD precharge of I/O bus lines 13 and 14. Also, N-channel MOS transistors 71, 81 are turned on in response to the clock .phi.WDT. Therefore, assuming that the transistors 71 and 81 happen to assume less conductive than the transistors 72 and 82, the potential of lines 31 and 32 can be higher than each threshold voltage of N-channel MOS transistors 75 and 85 and consequently, due to the conduction of N-channel MOS transistors 75 and 85, precharge of I/O bus lines 13 and 14 can not be accomplished. Also, the conduction of transistors 71,72,81 and 82 results in wasteful power consumption.